NXP Semiconductors /MIMXRT1062 /IOMUXC /SW_MUX_CTL_PAD_GPIO_EMC_32

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Interpret as SW_MUX_CTL_PAD_GPIO_EMC_32

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SEMC_DATA10 of instance: semc

1 (ALT1): Select mux mode: ALT1 mux port: FLEXPWM3_PWMB01 of instance: flexpwm3

2 (ALT2): Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7

3 (ALT3): Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: ccm

4 (ALT4): Select mux mode: ALT4 mux port: CSI_DATA21 of instance: csi

5 (ALT5): Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3

8 (ALT8): Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_EMC_32

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